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orderin g numbe r : ena1600 bi-cmos ic saturated driver with 2 channels + constant current driver LV8481CS overview the LV8481CS is low-voltage motor driver with a saturate d driver with 2 channels + constant current driver. since it is in wafer level package, this ic is optimi zed for t h e stepping motor driver and shutter driver of various portable equipments including the mobile phones with camera. functions ? saturated driver h bridge with 2 channels + constant current driver. ? i 2 c bus interface ? bu ilt-in af stepping motor sequence logic (ena b ling 2-phase excitation and 1-2 phase excitation) ? bu ilt-in lens home position sequence logic ? enabling power-saving by mos process ? built-in 4 bit dac for constant current ? bu ilt-in constant current detection resistance ? w afer level packag e. w l p10 (0.97mm 2.47mm 0.5mmt) ? bu ilt-in thermal shutdown circuit and lvs circuit. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc , vm max 5. 0 v output applied voltage v out max out1, out2, out3, out4, out5 5.0 v input applied voltage v in max ena, scl , sda -0.3 to +5.0 v gnd pin flow-out current ignd per channel 400 ma allowable power dissipation pd max with specified substrate * 550 mw operating temperature topr -30 to +85 c storage temperature tstg -40 to +150 c * specified substrate : 50.0mm 50.0mm 1.6mm, glass epoxy 1 layers printed circuit board specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. d0209 sy pc 20091020-s00001 no.a1600-1/13
LV8481CS no.a1600-2/13 allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc 2.4 to 4.5 v high level input voltage v ih 0.4 v cc to v low level input voltage v il ena, scl and sda to v cc 0. 13 v electrical characteristics at ta = 25c, v cc = 2.8v ratings parameter symbol conditions min typ max unit i cco en = 0v 0.1 1 ua supply current i cco 1 en = 3v 1.2 1.8 ma ron11 v cc = 3.0v (sum of the upper and lower side outputs) en = 3.0v, i out = 100ma 2.7 3.3 output on resistance 1 (out1 to out3) ron12 v cc = 4.5v (sum of the upper and lower side outputs) en = 3.0v, i out = 100ma 2.1 2.6 ron21 v cc = 3 .0v (sum of the upper and lower side outputs + rf (0.5 )) en = 3.0v, i out = 100ma 2.7 3.2 output on resistance 2 (out4 to out5 + sence r) ron22 v cc = 4 .5v (sum of the upper and lower side outputs + rf (0.5 )) en = 3.0v, i out = 100ma 2.1 2.55 output constant current dac1 i out 1 d3-d0code : 0000 260 ma output constant current dac2 i out 2 d3-d0code : 0001 250 ma output constant current dac3 i out 3 d3-d0code : 0010 240 ma output constant current dac4 i out 4 d3-d0code : 0011 230 ma output constant current dac5 i out 5 d3-d0code : 0100 220 ma output constant current dac6 i out 6 d3-d0code : 0101 210 ma output constant current dac7 i out 7 d3-d0code : 0110 200 ma output constant current dac8 i out 8 d3-d0code : 0111 190 ma output constant current dac9 i out 9 d3-d0code : 1000 180 ma output constant current dac10 i out 10 d3-d0code : 1001 170 ma output constant current dac11 i out 11 d3-d0code : 1010 160 ma output constant current dac12 i out 12 d3-d0code : 1011 150 ma output constant current dac13 i out 13 d3-d0code : 1100 140 ma output constant current dac14 i out 14 d3-d0code : 1101 130 ma output constant current dac15 i out 15 d3-d0code : 1110 120 ma output constant current dac16 i out 16 d3-d0code : 1111 110 ma output turn on time traise out1-out4 1 3 us output turn off time tfall out1-out4 0.2 1 us af pls period taf 1.8 2 2.2 ms input curren i in v in = 3v 0 1 ua sda pin low level output v ol i o = 300ua 0.2 0.3 v ti 2 csh i 2 c comand sh operation 10 us ti 2 caf i 2 c comand af sequence operation 1.2 ms time of onset of movements after receiving i 2 c communication ti 2 cdp i 2 c comand defaultposition sequence operation 6 ms thermal shut down operation temperature ttsd ena = 3v design target value 175 c hysteresis t tsd ena = 3v design target value 35 c (assured design target) * : design target val ue, not to be measured at production test.
LV8481CS package dimensions unit : mm (typ) 3362 sanyo : wlp10(2.47x0.97) 2.47 0.97 0.5 max 0.14 top view side view side view bottom view 0.5 0.235 12345 0.5 0.235 0.27 pd max -- ta 0 0.29 0.4 0.6 0.2 0.8 --30 60 90 30 0 120 0.55 ambient temperature, ta - c allowable power dissipation, pd max - w specified board:50.0 50.0 1.6mm 3 glass epoxy pin assignment 54321 a b ball side view 1pin mark 2.47 0.5 0.5 0.97 pin no. pin name a1 out5 a2 v cc a3 ena a4 sda a5 scl b1 gnd b2 out4 b3 out3 b4 out2 b5 out1 12345 top view a b 1pin mark out5 v cc ena sda scl gnd out4 out3 out2 out1 no.a1600-3/13
LV8481CS block diagram i 2 c interface s/p conversion control ena out1 out2 out3 out4 out5 r_sense r_sense af gnd sh v cc v cc v cc 1.3v scl sda 4bit dac lvs tsd + - + - no.a1600-4/13
LV8481CS serial bus communication specifications i 2 c serial transfer timing conditions standard mode th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbus toff standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz ts1 setup time of scl with respect to the falling edge of sda 4.7 us ts2 setup time of sda with respect to the rising edge of scl 250 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 4.0 us th1 hold time of sda with respect to the falling edge of sda 4.0 us data hold time th2 hold time of sda with respect to the falling edge of scl 0 us twl scl low period pulse width 4.7 us pulse width twh scl high period pulse width 4.0 us ton scl, sda (input) rising time 1000 ns input waveform conditions toff scl, sda (input) falling time 300 ns bus free time tbus interval between stop condition and start condition 4.7 us high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 400 khz ts1 setup time of scl with respect to the falling edge of sda 0.6 us ts2 setup time of sda with respect to the rising edge of scl 100 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 0.6 us th1 hold time of sda with respect to the falling edge of sda 0.6 us data hold time th2 hold time of sda with respect to the falling edge of scl 0.08 us twl scl low period pulse width 1.3 us pulse width twh scl high period pulse width 0.6 us ton scl, sda (input) rising time 300 ns input waveform conditions toff scl, sda (input) falling time 300 ns bus free time tbus interval between stop condition and start condition 1.3 us no.a1600-5/13
LV8481CS i 2 c bus transmission method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. ts2 th2 scl sda when data is not being transferred, both scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nde d when sda is changed from low to high while scl is high. th1 th3 scl sda start condition stop condition data transfer and acknowledgement response after the start condition has been generated, the data is tr ansferred on e byte (8 bits) at a time. generally, in an i 2 c bus, a unique 7-bit slave address is assigned to each device, and the firs t byte of the transfer data is allocated to the 7-bit slave address and to the command (r/w) indicating the transfer direction of the subsequent data. every time 8 bits of data for each byte are transferred, the ac k signal is sent from the receiving end to the sending end. immediately after the clock pulse of scl bit 8 in the data transferred has fallen to low, sda at the sending end is released, and sda is set to low at the receiving en d, causing the ack signal to be sent. when, after the receiving end has sent the ack signal, the tran s fer of the next byte remain s in the receiving status, the receiving end releases sda at the fa lling edge of the ninth scl clock. m s b l s b a c k l s b a c k m s b m s b l s b a c k w data rw : 1/0 s7 scl sda (write) data slave address 3rd byte 1st byte start stop s6 s5 s4 s3 s2 s1 rw a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 number of slave address is 0110010. (s7 s1) no.a1600-6/13
LV8481CS no.a1600-7/13 serial map register a ddress data a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 afmode [7 : 0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fl afmode [5 : 3] hold time set [2 : 0] 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 shmode [2 : 0] 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 currentmode [3 : 0] 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 upper : register name lower : default value *caution : address 00000111 is ic test mode. thi s address is out of use. serial each mode settings rotational direction setting 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d0 rotational dire ction 0 cw 1 ccw af on/off setting 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d1 on/off 0 standby mode 1 operation mod e af counter reset 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d2 counter rese t 0 reset on 1 reset o ff
LV8481CS no.a1600-8/13 step number setting 0 0 0 0 0 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 (32p) d6 (16p) d5 (8p) d4 (4p) d3 (2p) number of steps 0 0 0 0 0 2step 0 0 0 0 1 4step 0 0 0 1 0 6step 0 0 0 1 1 8step 0 0 1 0 0 10step 0 0 1 0 1 12step 0 0 1 1 0 14step 0 0 1 1 1 16step 0 1 0 0 0 18step 0 1 0 0 1 20step 0 1 0 1 0 22step 0 1 0 1 1 24step 0 1 1 0 0 26step 0 1 1 0 1 28step 0 1 1 1 0 30step 0 1 1 1 1 32step 1 0 0 0 0 34step 1 0 0 0 1 36step 1 0 0 1 0 38step 1 0 0 1 1 40step 1 0 1 0 0 42step 1 0 1 0 1 44step 1 0 1 1 0 46step 1 0 1 1 1 48step 1 1 0 0 0 50step 1 1 0 0 1 52step 1 1 0 1 0 54step 1 1 0 1 1 56step 1 1 1 0 0 58step 1 1 1 0 1 60step 1 1 1 1 0 62step 1 1 1 1 1 64step note): d3 : 2pulse on/off (2step) setting register d4 : 4pulse on/off (4step) setting register d5 : 8pulse on/off (8step) setting register d6 : 16pulse on/off (16step) setting register d7 : 32pulse on/off (32step) setting register
LV8481CS no.a1600-9/13 af holdtime setting 0 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 d2 d1 d0 hold pulse number 1 (at af sequence) hold pulse number (at default position sequence) 0 0 0 1puls (2msec/1msec) 1puls (10msec/5msec) 0 0 1 2puls (4msec/2msec) 2puls (20msec/10msec) 0 1 0 4puls (8msec/4msec) 4puls (40msec/20msec) 0 1 1 5puls (10msec/5msec) 5puls (50msec/25msec) 1 0 0 8puls (16msec/8msec) 8puls (80msec/40msec) 1 0 1 16puls (32msec/16msec) 16puls (160msec/80msec) 1 1 0 32puls (64msec/32msec) 32puls (320msec/160msec) 1 1 1 1puls (2msec/1msec) 1puls (10msec/5msec) note) : holdtime value make a written (2-p hase excitation/1-2 phase excitation). af excitation setting 0 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 d3 excitation sy stem 0 2-phase ex citation 1 1-2 phase excitation default position sequence setting 0 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 d4 on/off 0 off 1 default position sequence on default position and af sequence + steps setting 0 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 d5 +64step ( on/off) 0 off 1 +64step further note : when the pulses of 64 steps or more in total are set in default position sequence and af sequence and the flag of d5 is ?1?, the pulse of the number of afsteps + 64steps can be set. af sequence and default position sequence flag 0 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 the situation between standby state and under executio n of the sequences af and default position can be confirmedin the state of ?d7?. d7 fl 0 standby st ate 1 under ex ecution when the sequence ends, fl automatically becomes zero.
LV8481CS af sequence diagram hold time standby (current-carrying off) target position hold- current-carrying i 2 c control signal reception af sequence end hold time driver operation lens stroke position hold- current-carrying by target steps step operation current-carrying off (1) set default value at out1 = h, out2 = l, out3 = h and out4 = l. (2) stmspeed at the af sequence becomes 500pps. (3) the hold current-carrying time, it is the same time both front and rear times. default position sequence diagram hold time hold time standby (current-carrying off) default position hold-current-carrying hold current-carrying i 2 c control signal reception default position sequence end driver operation lens default position lens position to the lens default position, step operation current- carrying off further note : (1) when the flag of d4 in the address 0000000 1 of a d efault position sequence is ?1?, whether or not the total of a default position sequence is 65step or more is set by using a flag in d5. the command is transmitted by the i 2 c communication after setting hold time. (2) the number of step, the rotati o nal direction and afon/off are set in the address 00000000. and, a default position sequence is performed at the ic side when the data is transmitted by using i2c communication. (3) stmspeed in a default position sequence becomes 100pps. (4) hold current-carrying time, it becomes co n gruent with the previous or nest time. no.a1600-10/13
LV8481CS no.a1600-11/13 sh bridge, out4 to 5 operation setting 1 0 0 0 0 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 out4 out5 bridge state 0 0 z z standby all channels off 0 1 h l constant current between out4 and out5 1 0 l h constant current between out5 and out4 1 1 l l brake logic ? constant current is driven when applying current between channels out4 and out5. sh bridge, on/off setting 1 0 0 0 0 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 d2 on/off 0 standby 1 operation constant current setting 1 0 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 d3 d2 d1 d0 constant current value 0 0 0 0 260ma 0 0 0 1 250ma 0 0 1 0 240ma 0 0 1 1 230ma 0 1 0 0 220ma 0 1 0 1 210ma 0 1 1 0 200ma 0 1 1 1 190ma 1 0 0 0 180ma 1 0 0 1 170ma 1 0 1 0 160ma 1 0 1 1 150ma 1 1 0 0 140ma 1 1 0 1 130ma 1 1 1 0 120ma 1 1 1 1 110ma
LV8481CS af sequence (2-phase excitation drive) (1 cycle = 4clk) no.a1600-12/13 af sequence (1-2 phase excitation drive) (1 cycle = 8clk) a position l1 l2 af sequence abcdefgha (clockwise direction) 100% 0 -100% 100% 0 -100% 100% 0 -100% 100% 0 -100% clk bcde f ghabcd d position l1 l2 af sequence abcda (clockwise direction) clk abcda
LV8481CS sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of december, 2009. specifications and inform ation herein are subject to change without notice. ps no.a1600-13/13

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